For most of the history of computing, a new processor technology has not eliminated the processor that preceded it. Instead, computer architecture has evolved by adding increasingly specialized forms of computation and determining how they can work together.

The CPU did not disappear when GPUs became powerful enough to perform artificial intelligence computation. Instead, the CPU evolved into a partner to the GPU. NVIDIA’s new Vera CPU provides an unusually clear example. AMD is moving in a similar direction by combining EPYC processors with Instinct GPUs in its Helios rack-scale architecture. Intel likewise continues developing increasingly specialized CPU and accelerator architectures.

Quantum computing now appears likely to add another layer.

The future high-performance computer may therefore be neither a classical computer nor an AI computer nor a quantum computer.

It may be all three.

A future system could contain enormous populations of CPUs, GPUs and quantum processing units, or QPUs, connected through a hierarchy of extremely high-speed interconnects and managed as a heterogeneous computing system. “Heterogeneous” simply means that different kinds of processors perform the work for which each is best suited.

The most interesting development may be that the QPU layer itself does not necessarily have to consist of one kind of quantum processor.

NVIDIA is developing an architecture that could allow quantum processors employing very different qubit technologies—and potentially QPUs from different manufacturers—to participate in the same broader accelerated-computing environment.

That begins to suggest a fundamentally different model for the computer of the future:

CPU + GPU + QPU + networking + memory + orchestration software = one computing system.

And eventually the QPU portion of that equation might itself become:

superconducting QPUs + trapped-ion QPUs + neutral-atom QPUs + photonic QPUs + silicon-spin QPUs + topological QPUs.

The important question may therefore cease to be which processor replaces the others.

It becomes: Which processor should perform each particular part of the computation?

Vera Demonstrates What Is Already Happening to the CPU

NVIDIA’s Vera CPU is important in understanding this transition because it demonstrates that NVIDIA does not expect the GPU to eliminate the CPU.

NVIDIA has instead designed its own Olympus CPU core specifically for the emerging AI computing environment.

A Vera Rubin NVL72 rack combines 36 Vera CPUs and 72 Rubin GPUs. The Vera CPUs collectively provide 3,168 Olympus CPU cores, while the Rubin GPUs supply the massively parallel computation required for AI training and inference. NVIDIA connects them through extremely high-bandwidth coherent interconnects so they increasingly operate as components of a larger computer rather than isolated processors. (NVIDIA)

Vera is particularly optimized for high single-threaded performance, memory movement and the sequential workloads generated by agentic AI.

That is important because an AI agent does not spend all its time performing neural-network mathematics.

It may call a model on a GPU, execute Python code on a CPU, query a database, retrieve information, compile software, communicate across a network and then return the result to the GPU for another inference operation.

The computing cycle increasingly resembles:

GPU → CPU → GPU → CPU → GPU.

Making the GPU dramatically faster therefore eventually exposes the CPU as another potential bottleneck.

The solution is not eliminating the CPU.

It is improving it and integrating it more closely with the GPU.

AMD Is Reaching a Similar Architectural Conclusion

NVIDIA is not alone in moving toward rack-scale heterogeneous computing.

AMD’s new Helios architecture integrates 72 Instinct MI455X GPUs with EPYC “Venice” CPUs and Pensando Vulcano networking. The MI455X uses AMD’s fifth-generation CDNA architecture and was launched in July 2026. AMD specifies approximately 40.3 PFLOPS of peak MXFP4 performance per MI455X accelerator. (AMD)

Helios therefore demonstrates the same larger architectural movement.

AMD’s approach differs from NVIDIA’s in important ways, particularly its greater emphasis on open standards such as UALink and Ultra Ethernet. But both companies increasingly treat the rack rather than the individual processor as the computing unit.

The competitive environment is consequently changing from:

AMD CPU versus Intel CPU

and later:

AMD GPU versus NVIDIA GPU

toward:

Who can construct the most effective complete heterogeneous computing system?

Quantum computing could expand that competition enormously.

The QPU Is Not a Faster CPU

The most important thing to understand about quantum computing is that a QPU is not simply an extremely fast replacement for a CPU.

Quantum processors exploit properties of quantum mechanics including superposition, interference and entanglement to perform certain classes of computation differently from classical machines.

Those characteristics potentially make quantum computers extraordinarily useful for particular problems involving quantum simulation, chemistry, materials science, optimization and certain mathematical operations.

But they do not make the QPU the ideal processor for running an operating system, processing an ordinary database query, serving a web page or executing most conventional software.

Likewise, a GPU is extraordinarily efficient at highly parallel numerical computation but is not generally the ideal processor for every sequential computing operation.

Future systems therefore appear increasingly likely to divide computation among specialized processors.

The CPU performs complex sequential and general-purpose work.

The GPU performs massive parallel numerical and AI computation.

The QPU performs particular quantum algorithms where quantum mechanics provides an advantage.

NVIDIA Is Building Around the QPU Rather Than Building the QPU

This is where NVIDIA’s quantum strategy becomes particularly interesting.

NVIDIA has not announced its own physical QPU.

Instead, it is attempting to provide much of the computational architecture surrounding quantum processors.

The foundation is CUDA-Q, NVIDIA’s open-source quantum development platform.

CUDA-Q is explicitly QPU-agnostic and qubit-agnostic. NVIDIA says applications can use CPU, GPU and QPU resources together from a common programming environment, while the underlying quantum computation can run either on quantum simulators or physical QPUs from different manufacturers. NVIDIA says CUDA-Q already integrates with approximately 75% of publicly available QPUs. (NVIDIA Developer)

This is potentially strategically important.

NVIDIA does not necessarily have to predict which qubit technology ultimately wins.

It can attempt to support many of them.

NVQLink Creates the Bridge to Quantum Hardware

NVIDIA’s NVQLink architecture extends this concept into hardware.

NVQLink tightly couples GPU-accelerated classical computers with quantum processors. NVIDIA currently specifies up to 400 gigabits per second of GPU-QPU throughput and less than 4 microseconds round-trip latency in its reference architecture. (NVIDIA)

That low latency matters because useful quantum computers cannot simply be treated as remote accelerators that receive a job and eventually return an answer.

Quantum processors require continual interaction with classical computers.

Qubits are extraordinarily susceptible to errors. Their state must be measured, the resulting information interpreted, errors identified and corrective actions determined quickly enough to keep the quantum computation functioning.

Consequently, a future fault-tolerant quantum computer could generate enormous streams of measurement information that must be processed by classical hardware in real time.

NVIDIA is positioning the GPU as part of that control system.

NVQLink therefore provides more than a data connection.

It provides a bridge between quantum computation and accelerated classical computation.

NVIDIA Ising Adds Artificial Intelligence to Quantum Control

NVIDIA has now added another fascinating layer: NVIDIA Ising.

The terminology needs to be understood carefully.

Ising is not an NVIDIA quantum processor.

It is a family of open AI models designed to help operate quantum processors.

The initial Ising family addresses two particularly difficult problems: QPU calibration and quantum error-correction decoding. (NVIDIA Developer)

Calibration is necessary because quantum hardware is extremely sensitive. Qubits must continually be tuned as physical conditions and device characteristics change.

NVIDIA’s Ising Calibration uses AI to interpret information coming from quantum hardware and automate parts of this tuning process.

Ising Decoding addresses quantum error correction.

A fault-tolerant quantum computer must repeatedly determine whether errors have occurred in its physical qubits and determine how those errors should be corrected without destroying the quantum information being protected.

That creates an enormous classical-computing problem.

NVIDIA says quantum-error-correction systems can require terabytes of qubit measurement information to be processed thousands of times per second. (NVIDIA)

GPUs are particularly attractive for this workload because the decoding process can contain substantial parallel computation.

NVIDIA’s newest Ising Decoding work has demonstrated more than a 300-fold improvement in logical error rate compared with one reference decoder under a specific color-code test condition while also producing substantially faster runtime. These are specialized experimental results rather than proof that one decoder universally dominates every QEC approach, but they demonstrate the potential role of AI and GPU acceleration in quantum control. (NVIDIA Developer)

The architecture therefore becomes even more interesting:

QPU generates quantum measurements → GPU executes AI-assisted error decoding → classical control determines the response → QPU continues computing.

Artificial intelligence becomes part of operating the quantum computer itself.

Different QPUs Could Potentially Perform Different Jobs

This architecture creates an intriguing possibility.

There may never be a single universally superior QPU.

Today’s quantum industry is pursuing radically different physical approaches.

IonQ and Quantinuum are developing trapped-ion systems.

QuEra develops neutral-atom systems.

Rigetti and IQM develop superconducting quantum processors.

Pasqal uses neutral atoms.

Oxford Quantum Circuits develops superconducting systems.

Quantum Motion and others are pursuing silicon-based approaches.

Other companies are developing photonic and still other quantum technologies.

NVIDIA’s NVQLink ecosystem already includes many of these companies and quantum-control-system manufacturers. (NVIDIA)

Different quantum technologies have different characteristics involving gate speed, coherence time, connectivity, fidelity, operating environment and scalability.

That raises a possibility that resembles today’s heterogeneous classical computer.

Instead of requiring one QPU technology to defeat every competitor, future quantum supercomputers could conceivably contain different QPU classes optimized for different quantum workloads.

This remains a future architectural possibility rather than an announced NVIDIA product.

But CUDA-Q and NVQLink are being designed in a manner that makes heterogeneous QPU integration considerably more plausible.

A future scheduler might therefore determine:

This operation belongs on the CPU.

This tensor calculation belongs on the GPU.

This quantum simulation belongs on one QPU architecture.

This optimization problem belongs on another.

The programmer might eventually interact with the complete computing environment rather than manually selecting every processor.

From Thousands of GPUs to Thousands of QPUs

Scale this architecture beyond a single rack and the implications become enormous.

Today’s AI factories already contain tens of thousands and, in the largest deployments, potentially hundreds of thousands of GPUs.

There is no fundamental architectural reason why future hybrid supercomputers must contain only one QPU connected to those resources.

If quantum hardware becomes sufficiently scalable and useful, a future data center could conceivably contain enormous numbers of CPU cores, GPUs and QPUs.

That does not mean today’s QPUs are remotely ready for such deployment.

They are not.

The point is architectural.

NVIDIA is developing software and interconnect technology that could allow the quantum layer to scale alongside classical accelerated computing rather than exist as an isolated scientific instrument.

CUDA-Q provides the programming abstraction.

NVQLink provides the real-time connection.

GPUs provide massive classical parallel processing.

Ising provides AI-assisted calibration and error decoding.

CPUs provide general-purpose computation and orchestration.

The QPU provides quantum computation.

Together they begin to describe something considerably more interesting than a quantum computer.

They describe a quantum-accelerated heterogeneous supercomputer.

Microsoft’s Majorana Strategy Attacks the Problem From the Other Direction

Microsoft is approaching the quantum problem differently.

Instead of concentrating primarily on the classical infrastructure surrounding third-party QPUs, Microsoft is developing its own quantum hardware.

Its Majorana 1 processor is based on Microsoft’s proposed topological-qubit architecture.

Microsoft says the chip currently contains eight topological qubits and that its underlying Topological Core architecture is designed eventually to support as many as one million qubits on a chip. Microsoft is also participating in DARPA’s program to develop a fault-tolerant quantum-computing prototype. (Microsoft Azure)

The attraction of topological quantum computing is potentially profound.

Rather than relying entirely upon software and enormous numbers of physical qubits to protect quantum information, Microsoft hopes the physics of the topological qubit itself can provide greater inherent protection against certain errors.

If successful at scale, that could dramatically change the economics and complexity of fault-tolerant quantum computing.

But Microsoft’s approach carries substantial technological risk precisely because the underlying physics and engineering are so ambitious.

Microsoft is essentially attempting to improve the QPU itself so fundamentally that fault tolerance becomes easier.

NVIDIA is addressing another part of the problem: regardless of which QPU technology succeeds, how do we connect it to enough classical computation to control it, correct it and use it?

These strategies are therefore not necessarily competitors.

A future Microsoft topological QPU could conceptually still participate in a larger heterogeneous classical-quantum architecture.

Google Willow Represents Yet Another Path

Google’s Willow processor represents another major approach.

Willow contains 105 superconducting qubits. Its most important achievement is not simply its qubit count but Google’s demonstration of below-threshold quantum error correction: as Google increased the size of its encoded logical qubit, the logical error rate decreased rather than increased. (blog.google)

That is a critical requirement for building large fault-tolerant quantum computers.

Google has subsequently continued improving Willow. Google reported in late 2025 that the full 105-qubit array achieved approximately 99.97% single-qubit gate fidelity, 99.88% entangling-gate fidelity and 99.5% readout fidelity. (blog.google)

Google’s long-term challenge is therefore to extend this progress from hundreds of physical qubits toward the much larger populations of physical and logical qubits required for commercially useful fault-tolerant quantum computation.

Once again, however, a large Google-style superconducting quantum computer would still require substantial classical computation for control, decoding and interaction with conventional applications.

That is precisely the architectural layer NVIDIA is attempting to address.

Quantum Error Correction May Become an AI Workload

One of the most fascinating possibilities is that AI and quantum computing could become mutually dependent.

Quantum computing may eventually accelerate certain AI calculations.

But AI may also be required to operate large quantum computers.

NVIDIA’s Ising project demonstrates this second possibility.

A sufficiently large QPU could continuously generate enormous quantities of error-syndrome and calibration information.

Machine-learning models running on GPUs could analyze that information.

The GPU could determine likely error patterns.

The CPU could coordinate the larger application and classical software environment.

The QPU could continue executing quantum operations.

Instead of quantum computing replacing AI hardware, AI hardware becomes part of the quantum computer’s control system.

NVIDIA has already demonstrated this concept with Quantinuum. Using NVQLink with Quantinuum’s Helios QPU and an NVIDIA Grace Hopper system, the companies demonstrated real-time quantum-error decoding with median decoding latency measured at approximately 67 microseconds in the reported experiment and a 5.4-fold improvement in error rate. (NVIDIA Developer)

This is an early implementation of a much larger architectural concept.

The Computer Is Becoming a Hierarchy of Specialized Processors

The historical progression is therefore revealing.

Early computers depended overwhelmingly on CPUs.

GPUs were originally added primarily for graphics.

GPUs evolved into massively parallel general-purpose accelerators.

Machine learning transformed GPUs into the dominant processor for AI computation.

But instead of eliminating CPUs, increasingly powerful GPUs created demand for CPUs better optimized to feed and coordinate them.

Vera is NVIDIA’s response.

AMD’s Helios architecture demonstrates the same system-level trend.

Quantum processors now add another specialized computational domain.

But instead of eliminating CPUs and GPUs, QPUs may actually create greater demand for both.

The CPU may orchestrate the application.

The GPU may execute AI and massive parallel computation.

The GPU may also decode quantum errors.

The QPU may perform specialized quantum algorithms.

Networking and interconnect systems move information among them.

Software decides where each operation belongs.

The Future Computer May Be Defined by Orchestration

This leads to perhaps the most important conclusion.

The decisive technology in future computing may not be any single processor.

It may be the orchestration layer that determines how all of them work together.

A future computer could contain tens of thousands of CPUs, hundreds of thousands of GPUs and eventually large populations of QPUs employing several different quantum technologies.

No human programmer could efficiently micromanage every operation across such a system.

The software architecture would need to determine dynamically where computation should occur based on latency, precision, energy consumption, cost, error rate, processor availability and the characteristics of the problem.

AI itself could increasingly perform this orchestration.

That would represent an important evolution from today’s computer.

Instead of writing software for a processor, programmers may increasingly describe a computational objective to a heterogeneous computing platform.

The system would determine how to divide the work among CPU, GPU and QPU resources.

New Technologies Rarely Eliminate the Old Ones

Computing history repeatedly demonstrates that a new technology often changes the role of an older technology without eliminating it.

Mainframes survived the personal-computer revolution.

Personal computers survived the rise of cloud computing.

CPUs survived the rise of GPUs.

GPUs are unlikely to disappear because of quantum computers.

And quantum processors are unlikely to replace general-purpose classical computers.

Each technology survives because each performs certain kinds of work exceptionally well.

What changes is the architecture surrounding it.

Vera is an excellent example. The rise of the GPU did not cause NVIDIA to abandon CPU development. It caused NVIDIA to design a CPU specifically suited to an accelerated AI computer.

Quantum computing may produce the next iteration of exactly the same process.

Microsoft is attempting to build a fundamentally different QPU around topological physics.

Google is advancing superconducting quantum processors such as Willow toward increasingly reliable logical qubits.

Numerous other companies are developing trapped-ion, neutral-atom, photonic, silicon-spin and superconducting alternatives.

NVIDIA is taking a different position. Rather than betting exclusively on one quantum technology, it is constructing CUDA-Q, NVQLink, Ising and accelerated classical computing infrastructure around the emerging QPU ecosystem. (NVIDIA Developer)

That could ultimately prove to be a remarkably powerful position.

The winning quantum processor may not be one processor at all.

Different QPUs may ultimately become specialized accelerators for different computational problems, just as CPUs and GPUs already occupy different roles.

The computer of the future may therefore not be a quantum computer replacing a classical computer.

It may be an enormous heterogeneous machine in which classical processing, artificial intelligence processing and quantum processing coexist—potentially at data-center scale—with software and AI continuously deciding which computational engine should perform each operation.

The evolution from CPU to CPU-plus-GPU is already well underway.

The next architectural transition may be:

CPU + GPU + QPU.

And after that, perhaps:

CPU + GPU + many different classes of QPU, operating together as one computer.

The history of computing suggests that this is how technological revolutions usually occur. The new processor does not simply kill the old processor. It changes what the older processor is expected to do, forces it to evolve, and becomes another specialized component in an increasingly powerful computing system.

The future of computer architecture may therefore be defined not by replacement, but by specialization, integration and orchestration.